direct-mapped cache

problem is as follow:

For a direct-mapped cache design with a 64-bit address, the following bits of the address are used to access the cache. (1 word = 64-bits) Tag: 63-10 Index: 9-5 Offset: 4-0

I figured out that each block has size of 4 words, and cache has 32 lines. And here’s the additional problem:

For each reference, complete the following table. “Replace” represents which bytes replaced if any. r

and I got this solution, but I can’t understand why 0x1e is "Miss". As I understood, to determine Hit or Miss, I have to compare Index, then compare Tag. If block for index/Tag is not full, it hits. but references that both Tag and Index is 0x0 are only three before ox1e; 0x00, 0x04 and 0x10. Why does ox1e has Miss?