How can a CPU be busy during DMA access with burst mode transfer


During burst mode in a DMA access, the DMAC has control over the bus for the whole transfer session which includes DATA PREPARATION time as well as DATA transfer time, after the transfer is over, the DMA relinquish the system bus. So in the mean time, the cpu can neither fetch any instruction from the MAIN MEMORY, nor it can fetch any operand, it can atmost complete the instruction it was executing before if that don’t include the use of system bus. In the book I have seen as cpu busy percent is given by

Data preparation time/(data prep time + data transfer time) How can the cpu be busy during the data preparation time when the bus is not with it. This can be the concept behind CYCLE STEAL mode, since it gains the bus only during data transfer, but how during burst mode??