64 byte cache block and memory overhead for cachline with 7 states (3 bits)

I came across some lecture notes of a professor about memory consistency and models. There is an example about memory overhead:

The cache line has 7 states (3 bits): unowned, shared, exclusive, modified, read, update and “uncached read”.

  • For 64 processor with the cache line described above, the memory overhead is 12.5%
  • For 256 processor with the cache line described above, the memory overhead is 50%
  • For 1024 processor with the cache line described above, the memory overhead is 200%.

This is the only information that I received from the notes. I wanted to ask him by contacting him but I got no answer. How are these overheads calculated?

Computer Architecture, Cache Memory question

A computer system has the following characteristics. The main memory has 1000 blocks. One block contains 8 words. Cache memory has 32 words. a)What is the format of the address? b)A program passes 4 times through the locations 7 to 37 decimally. What is the hit rate? And how does the cache look after the 4 passings. The system uses direct mapping.

I know that there are 1000 * 8 = 2^10 * 2^3 = 15 bits for the address. Other than that I am stuck.

Thanks!

How to calculate the cache index and the tag field?

“For a memory organization with 2GB of main memory, 32K cache size, and cache organized as 8-byte-blocks, directed mapped:

Suppose you have an access to memory address 0x0005B432. What is the cache index? What is the tag field?”

Please help me, I don’t know how I am supposed to solve this exercise. Also I need to find the cache index and the tag field of following memory addresses: 0x0005B436 0x0005B438 0x0003B437

Large Memory Cache Issues

Hello linuxers,

I'm running a CentOS server (specs below) with 32 GB memory. My problem is 18.49 GB of the 32GB is used by cache. That seems to be a lot. Is that a good thing or cache is using too much? I'm running a cryptocurrency website. I cache a lot of stuff because I'm using API to pull cryptocurrency prices like the ones on this page: https://www.cryptozink.io/live-cryptocurrency-coins-prices/.

Is cache keeping the site from running out of memory or it's using too much and I should…

Large Memory Cache Issues

Direct mapped cache example

i am really confused on the topic Direct Mapped Cache i’ve been looking around for an example with a good explanation and it’s making me more confused then ever.

For example: I have

  • 2048 byte memory
  • 64 byte big cache
  • 8 byte cache lines with direct mapped cache how do i determine the ‘LINE’ ‘TAG’ and “Byte offset’?


  • i believe that the total number of addressing bits is 11 bits because 2048 = 2^11

  • 2048/64 = 2^5 = 32 blocks (0 to 31) (5bits needed) (tag)

  • 64/8 = 8 = 2^3 = 3 bits for the index

  • 8 byte cache lines = 2^3 which means i need 3 bits for the byte offset

so the addres would be like this: 5 for the tag, 3 for the index and 3 for the byte offset

Do i have this figured out correctly?

Calculate the number of blocks and size of main memory in words for fully-associative cache

In order to organise the cache, main memory is divided up into blocks, and each block contains a certain number of words. The cache is divided up into lines; a block can fit in one line. A cache line has control and tag bits, allowing the cache to be searched for the required word. Cache A is the single cache for a small main memory. Cache A has been organised in a particular way, giving the following control and tag bits for cache A lines: Tag (10-bits) Offset (7-bits)

How many blocks are there in the main memory that cache A is supporting?

What is the size of main memory in words?

Direct and Associate Cache – Offset, Index, and Tag

I have two questions:

An 8-kB (8192 bytes) direct-mapped cache has 16-byte lines.  The system has 64-bit addresses numbered from 0 on the right to 63 on the left.  Which bits are associated with the offset, index, and tag? 
A 16-kB (16384 bytes) 4-way set associative cache has 8-byte lines.  The system has 64-bit addresses numbered from 0 on the right to 63 on the left. Which bits are associated with the offset, index, and tag? 

For offset, it’s: tag bits = address bit length – exponent of index – exponent of offset, correct?

Then the Index for a direct mapped cache is the number of blocks in the cache, and the Tag bits are everything else, right?

How would I calculate these? Because I’m a little confused on an associated cache vs a direct-map cache.

Associative mapped cache, word addressable

I have an associative mapped cache with 10 tag bits and an offset of 7bits.

What is the size of each main memory block in words(word addressable) and main memory size in words?

i worked it out as: block size would 2^7bits. main memory would be 2^17bits.

the issue I am facing is, how do I get them to be word addressable with this much information given. I have managed to get the above result in byte-addressable. Please correct me if i am wrong.