How do you compute and compare the delays between a (4:2) compressor and (3,2) counter carry save tree?

My question: How is Table 6.8 shown below computed for different operands? For example, for 3 operands how did they compute:

Number of levels using (3,2) = 1

Number of levels using (4;2) = 1

Equivalent delay: 1.5

Or how about for 9 operands how did they compute:

Number of levels using (3,2) = 4

Number of levels using (4;2) = 3

Equivalent Delay: 4.5

The textbook also points out that the equivalent delay of a (4;2) compressor carry save tree with 9 operands (4.5) is bigger than that of a carry save tree using (3,2) counters. Why is that?

What are the general conditions when one is bigger than the other?

The following is an image of a (4:2) compressor taken from this book.

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The truth table provided for this compressor is:

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where $ a=b=c=1$ and $ d=e=f=0$ . I think these constants are used to generalize the circuit.

An adder tree that uses (4;2) compressors will have a more regular struc-ture and may have a lower delay than an ordinary CSA tree made of (3,2) counters. Table 6.8 compares the delays of carry-save trees using either (3,2) counters or (4;2) compressors. Since the delay of a (4;2) compressor is 1.5 times that of a (3,2) counter, the number of levels of (4;2) compressors in column 3 is multiplied by 1.5 to yield the equivalent delay in column 4. Note that the equivalent delay of a carry save tree using (4;2) compressors (column 4) is not always smaller than that of a carry save tree using (3,2) counters (column 2). For example, for nine partial products, (3,2) counters will yield a carry save tree with an overall lower delay. Various other counters and compressors can be employed in the implementation of the addition tree for the partial product accumulation; for example, (7,3) counters

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