My computer has 2 CPUs, each with 8 cores. However, when using parallel operation, only 8 cores of one CPU can be called. How can I set it so that 8 cores of the other CPU can also participate in the calculation?
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I am using Open MPI and C++ to try out simple programs on my laptop. When I use the 2 cores on my computer as processors, the program runs us expected. However, when I instead do –use-hwthread-cpus, it seams that I never get past the Barrier(). That is the only thing I am changing, just the way I start the program. It is the same .exe file running.
I am running Ubuntu 18.04 server. I have an Intel i9 9980xe CPU, which has 18 cores and 2 threads per core. But it shows that the CPU has only 15 cores in /proc/cpuinfo as well as in htop. Why?
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I’d like to have a bit more understanding of how, on a circuitry/hardware level, an assembler program works.
I think I have a very broad-brush understanding of how a CPU would process machine code on a hardware level. Please bear with me for this very generalised, hypothetical example:
If you took 00101110 in machine code, with the first part 0010 as an opcode and the second part 1110 as location address…
I think I understand, broadly, how those 8 bits of data would be fed along 8 wires to an instruction register, and how from there, the opcode 0010 gets fed along 4 wires into a variety of checking circuits to check the opcode, and a checking circuit would output true if if the opcode corresponded to the configuration of that circuit. Like this (yes I’ve been watching crash course computer science):
And i think I understand how, in broad terms, the location address 0111 would be sent along 4 wires that feed into multiplexors attached to four latch matrices, causing address location 0111 to be accessed in each of those matrices, each of which then feeds back whether its data bit at the location was a 1 or 0 / on or off.
What I’m saying is that I think I can begin to see, or at least imagine, how a processor ‘processes’ a binary number, on the level of hardware/circuitry, without it seeming like magic.
My question is, can someone explain to me on this level how a CPU, as part of an assembler, would translate assembly code?
For example, how would the circuitry take MOV EAX [EBX] and act on that as an instruction? I know that it would parse it, etc., but HOW does it parse it, on the level of wiring? Like how does it take a ‘MOV’ and translate that into the correct configuration of on/off wires?
On a related note, obviously the ‘MOV’ isn’t stored as ‘MOV’ in the computer’s memory – it’s stored in binary. So if it’s already stored in binary, why do we need to bother to translate it to a different binary configuration using an assembler?
I have a M620 and M640 i7 laptops. In virutal box, I can get the M640 to give me only 2 CPU’s for divide between guest (XP) and host (W7). On the M620, I can use 4 CPU’s on the guest of 8 available CPU’s. Both machines are the same Lenovo T510, and both show 2 CPU’s/4 threads on the processor spec’s.
The problem is with CPU usage. On the machine with only one CPU available, I max out CPU usage at 100% which completely hangs Windows Explorer with W7 operations. I don’t have the problem with the M620 machine, I can run duel processes on the XP and W7 without issue.
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I am running Ubuntu 18 on a System76 Oryx Pro 4 with an i7 8th gen 6 cores.
As you can see from the following image, when all CPUs usage is <= 6%, all CPUs run at a frequency of 800MHz.
However, as soon as I run an infinite while loop in a terminal which causes only CPU5 usage to increase to 100%, all CPUs (even those with 0% usage) scale to 4,100 MHz which is the maximum CPU freq.
Is this the expected behavior? Also, is there any way that the behavior can be changed so that only the frequency of the CPU with 100% usage increases to the top speed.