Consider the following code sequence that is executed on a processor that doesnt supports stalls and only supports ALU-ALU forwarding :
I1: lw $ 1, 40($ 6) I2: add $ 6, $ 2, $ 2 I3: sw $ 6, 50($ 1) I4: lw $ 5, -16($ 5) I5: sw $ 5, -16($ 5) I6: add $ 5, $ 5, $ 5
Now the only way to run this code on this processor is to insert nops . The solution is :
I1: lw $ 1, 40($ 6) I2: add $ 6, $ 2, $ 2 I22: nop I3: sw $ 6, 50($ 1) I4: lw $ 5, -16($ 5) I44: nop I45: nop I5: sw $ 5, -16($ 5) I6: add $ 5, $ 5, $ 5
My question is why between the instructions I2 and I3 ( Alu-Store hazards ) we inserted only one nop ? Why one nop is enough here ? According to my understanding since this hazard cant be supported through ALU-ALU forwarding then this is a hazard for this processor which means that the add must write first the result through the WB stage and then the SW instruction reads it from the Register file and therefore two nops are needed since in this case, the instance the add instruction is at its WB stage the SW is at its ID stage and through register file forwarding the SW can read then the register needed .
The problem I am stuck at requires me design a hazard free asynchronous sequential circuit for a given problem description. I have followed the routine steps as follows:
- I have obtained the primitive flow table from the problem description
- I have reduced the flow table using state minimisation routines of incompletely specified FSM
- I have assigned the output symbol preventing glitches
- I have done the state assignments of the reduced flow table
Let us assume that I require three secondary variables $ y_1,y_2 ,y_2 $ for the state encoding.
Now I have the resulting flow table. I am stuck at how I should proceed for hazard checking. I know the general procedure of checking and removing static and dynamic hazards, given a function and some transitions.
In this problem,
- For static hazards, I guess, I should check the KMap for each $ y_1 ,y_2,y_3 $ and thereby check for adjacent $ 1’s$ . Am I right?
- For dynamic hazards , I really have no clue how to proceed.Descriptive answers would be very helpful
Thank you in advance for all your answers.
The question is to find the hazards within Cycle 1 to 6 and their correct values, as well as the type of the harzards
so we know data hazards may occur on data that is not ready yet and we can solve them by forwarding data in between the pipes.
Look at this piece of code:
lw $ 6, -16($ 6) sw $ 6, -16($ 5)
sw wants the data that comes from the MEM read and it wants it just for the MEM write. So we can use a bypass to forward the output of the MEM to the input of the MEM (in the data write input) and this is solving the hazard without a bubble (nop).
Is it implemented into the MIPS core and if not, what will it do?
5 stage pipline
addi $ t1,$ zero,0x30 lw $ t2,0($ t1) sw $ t2,0xff18($ zero) addi $ t2,$ zero,100
Question is to find hazards existing in the code and the answer is:
- Hazard 1: Between lines 1 and 2. Register t1. Solved using forwarding.
- Hazard 2: Between lines 2 and 3. Register t2. Solved using forwarding.
But I found the answer is rather strange,
- So there is a hazard between line 1 and 2, in the first line t1 writes back in the fifth stage, and in the second line t1 uses in the decode stage, in my opinion there should be a stalling first and then forward to have access to t1 in the second line.
- I don’t see a hazard between line 2 and 3? line 2 t2 write back in the fifth stage, and line 3 fetches t2 in the first stage
Am I thinking something strange, why the correct answer seems not correct to me?
To be precise I am here for RAW hazard. Consider a 5 stage pipeline .
In case of $ I_4-I_1$ dependency , I am not sure if it is an $ RAW$ hazard as $ I_4$ does not depends on value of $ R_1$ that $ I_1$ gives. and even if it fetches it ,it still be a wrong value as per the instruction sequence as $ I_2$ is modifying it.
So , is $ I_4-I_1$ a $ RAW$ hazard ?
and if yes, then please give suitable explanation why so and related information about $ RAW$ hazard as it happened even if $ I_2$ modified the Value in between .
Hi everyone and first of all thank you for been reading. I’m a little confused about data hazard dependences when a “Store” instruction is followed by a “Load” instruction. (Assume that we’re working with a 5 stages pipeline processor withouth data forwading paths)
So if I have the following code now:
Store R3,R8,off-1 Load R3, off-2
If we’ve had ADD and Subsract instructions instead of “store” and “load” we’ll have data hazard dependences, so we would have to “wait” for the result using No-Op, but in this case; can I start “fetchig” the second instruction while the first one is on “Decode” stage?
I think I’m missing some concepts here, as to where the operand is fetched from and where it gets stored to.