why we need pipeline registers in pipeline processor ( as for example for MIPS processor )

I think the answer because the data of an instruction can be overridden by the data of the instruction that will be fetched after it , but I think the data of the first instruction will always be ahead ( in one stage further of the data of the next instruction ) since the data is always passed to the next stage at the clock edge so I think there will be no collision between the data of instructions ? Please someone explain using a small example to get the idea . Many thanks.

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The maximum decimal integer that can be stored in memory of 8-bit word processor computer?

Actually i am preparing for an exam and in the last year exam this que. was been asked. i.e

The maximum decimal integer number that can be stored in memory of 8-bit word processor computer ?

a) (128)10
b) (127)10
c) (129)10
d) (255)10

Answer of this que. as given in the answer key is (b). And I have no idea how they arrived at this result.

Acc. to my understanding, we have 8-bits, which is 28 = 256 so 255 should be the maximum integer which we can store.

Is this malware Gen:Variant.Fugrafa.15976 (B) [krnl.xmd] detected on NJStar Chinese word processor a false alarm?

I found this malware Gen:Variant.Fugrafa.15976 (B) [krnl.xmd] on NJStar Chinese word processor using Emisoft Emergency Kit to scan for malware. I have been using NJStar Chinese word processor for a long time and today is the first time I see this malware appearing during scan. I did a recent update of the virus definition.

I tried to google for more information on this malware but could not find anything. Could it be a false alarm?

Extracted from report;

C:\Program Files (x86)\NJStar Chinese WP6\update.dll    detected: Gen:Variant.Fugrafa.15976 (B) [krnl.xmd] 

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Which of these devices might slow down processor?

I have test question.

Which devices inside processor are used to speed up work indirectly i.e. program isn’t executing a code for that device?

Possible answers: DRAM | Cache | Pipeline | GPU | RAM | ARM | Stack | FPU

I think we can immediately say, that DRAM, GPU, & RAM is wrong picks, because they are not inside cpu – they are different parts of computer. Also stack is inside RAM, not CPU. So left answers are cache, pipeline, arm & fpu? Also not sure about floating point number.

What does it mean for a 16 bit processor that issues 24 bit address? [duplicate]

This question already has an answer here:

  • What all can be said when you say that the CPU is 32 bit? 1 answer

I was solving a problem from William Stallings’ 8th edition, in the cache memory section. It was question 4.6, and is as follows:

Given the following specifications for an external cache memory:
four-way set associative; line size of two 16-bit words; able to accommodate a total of 4K 32-bit words from main memory; used with a 16-bit processor that issues 24-bit addresses.
Design the cache structure with all pertinent information and show how it interprets the processor’s addresses.

I solved the question, however, I do not understand how can a 16 bit processor issue 24 bit address ? shouldn’t it issue 16 bit addresses ?

Also, the the previous question 4.5 which is as follows :

Consider a 32-bit microprocessor that has an on-chip 16-KByte four-way set-associative cache. Assume that the cache has a line size of four 32-bit words. Draw a block diagram of this cache showing its organization and how the different address fields are used to determine a cache hit/miss. Where in the cache is the word from memory location ABCDE8F8 mapped?

We consider that the address is 32 bits long. I was under the assumption we do this because the microprocessor is 32 bit.

Please clear this confusion for me. Can an n-bit processor only issue n-bit address or is it completely arbitrary?

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