understanding makefiles & their dependencies


In a practice question, I was supposed to derive a dependencies graph from a given make-file. I couldn’t find any relevant examples online but I attempted the following. Is this what is expected?

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all: prog x.o: x.cpp globals.hh $  (CC) -c x.cpp y.o: y.cpp globals.hh $  (CC) -c y.cpp prog: x.o y.o $  (LD) -o prog x.o y.o -lc 

Also, I would like to understand what happens if we repeat make all after altering either x.cpp or the headers file after.

From what I understand, if I run make all once and then change x.cpp, the following commands will be re-run:

$  (CC) -c x.cpp and -o prog x.o y.o -lc 

and in case of the headers file, I think all three will re-run when I do make all again. Am I correct? What would be the sequence?