why we need pipeline registers in pipeline processor ( as for example for MIPS processor )

I think the answer because the data of an instruction can be overridden by the data of the instruction that will be fetched after it , but I think the data of the first instruction will always be ahead ( in one stage further of the data of the next instruction ) since the data is always passed to the next stage at the clock edge so I think there will be no collision between the data of instructions ? Please someone explain using a small example to get the idea . Many thanks.